1. Field of the Invention
The present invention pertains to the field of integrated circuit devices. More particularly, this invention relates to a low capacitance memory cell for a fully associative content-addressable memory array.
2. Background
A typical content addressable memory (CAM) comprises an array of CAM cells. Each CAM cell in the array usually includes a static random access memory (SRAM) cell and comparator circuitry. The comparator circuitry of a CAM cell typically performs comparison between data stored in the SRAM cell and input data received over a corresponding set of bit lines. Each CAM cell is typically coupled to a match line. Typically, the comparator circuitry of the CAM cell generates a match signal on the match line if the input data on the bit lines matches the data stored in the CAM cell.
The CAM cells of a typical CAM array are arranged into a matrix of rows and columns. The CAM array usually includes a match line for each row of the CAM array. Each column of the CAM array typically shares a set of bit lines.
During a CAM look-up operation, each CAM cell in the CAM array that detects a mismatch discharges the match line row. The discharged voltage on the match line indicates a CAM mismatch for that row of the CAM array. Any one CAM cell in a row of the CAM array can indicate a mismatch for the entire row by discharging the corresponding match line.
FIG. 1 illustrates a prior CAM cell 10. The CAM cell 10 includes an SRAM cell comprising a pair of transistors Q2 and Q3 and a pair of inverters 20 and 22. The comparator circuitry of the CAM cell 10 comprises a set of transistors Q4-Q7. The transistors Q4 and Q5 and the transistors Q6 and Q7 are arranged as pass gates. The transistors Q4 and Q5 are a pass gate for input data received over a bit line 12. The transistors Q6 and Q7 are a pass gate for input data received over a bit line 14.
During a CAM look-up operation, if a mismatch occurs between the data received over the bit lines 12 and 14 and the data stored in the SRAM cell then the pass gate of the transistors Q4 and Q5 or the pass gate of the transistors Q6 and Q7 drive a node 24 to a voltage high. The high voltage at the node 24 switches on transistor Q1 which is the discharge transistor for a match line 18. The transistor Q1 then discharges the voltage on the match line 18 to indicate a failed CAM match.
The CAM cell 10 presents a high input capacitance at the bit lines 12 and 14. The input capacitance at the bit line 12 includes the diffusion capacitance's of the transistors Q4 and Q5. The input capacitance at the bit line 14 includes the diffusion capacitance of the transistors Q6 and Q7. In addition, if either of the pass gates of the transistors Q4 and Q5 or the transistors Q6 and Q7 is switched on, then the input capacitance at the bit line 12 or 14 also includes the gate capacitance at the transistor Q1 and the capacitance of charging the channels of the pass gate (Q6, Q7) which is equivalent to a gate capacitance of both transistors (Q6, Q7). Such high capacitance at the bit lines 12 and 14 increases the loading for circuitry that drives the bit lines 12 and 14 and slows down the CAM look-up operation.
FIG. 2 illustrates another prior CAM cell 30. The CAM cell 30 includes an SRAM cell comprising a pair of transistors Q10 and Q11 and a pair of inverters 40 and 42. The comparison and discharge functions for the CAM cell 30 are performed by a set of transistors Q12-Q15. The transistors Q12 and Q13 are serial transistors coupled to a match line 38. Similarly, the transistors Q14 and Q15 are serially coupled to the match line 38.
During a CAM look-up operation, if a mismatch occurs between the data received over a set of bit lines 32 and 34 and the data stored in the SRAM cell, then either the serial transistors Q12 and Q13 or the serial transistors Q14 and Q15 switch on and discharge the match line 38.
In this case, the match line 38 is heavily loaded. If the transistor Q12 is switched on, then the match line 38 is loaded by the diffusion of the drain of the transistor Q14, the diffusions of the source and the drain of the transistor Q12, the diffusion of the drain of the transistor Q13, and the channel of the transistor Q12 which is equivalent to a gate capacitance of the transistor Q12. Such a load is relatively large in comparison to the discharge strength of the CAM cell 30 provided by two serial transistors.
Furthermore, the high output capacitance for the CAM cell 30 is duplicated in all CAM cells along a row of such a prior CAM array. Such a high capacitive loading of the match line 38 limits the switching speed during a CAM look-up operation. The limited switching speed effectively imposes an upper limit on the number of CAM cells that may be placed along a row of such a prior CAM array, thereby limiting the bit width of the CAM.